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CXL1504M
CMOS-CCD 1H Delay Line for NTSC
Description The CXL1504M is a delay line used in conjunction with an external low-pass filter. Through negative phase input and positive phase output 1H delay time is obtained for NTSC signals. Features * Single 5V power supply * 14.3MHz driver * Low power consumption at 160mW (Typ.) * Built-in peripheral circuits * Completely adjustment free Functions * 905.5-bit CCD register * Clock driver * Autobias circuit * Input clamp circuit * Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Voltage Range (Ta = 25C) Supply voltage VDD 20 pin SOP (Plastic)
6 -10 to +60 -55 to +150 500
V C C mW
5 5%
V
Recommended Clock Conditions (Ta = 25C) * Input clock amplitude VCLK 0.3 to 1.0 * Clock frequency fCLK 14.318182 * Input clock waveform sine wave Input Signal Amplitude VSIG 560
Vp-p (0.5Vp-p typ.) MHz
mVp-p (Max.)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E71217A78-PS
CXL1504M
Block Diagram and Pin Configuration (Top View)
SUB CLK VDD VDD VSS VSS
11 10
NC
NC
NC
20
19
18
17
16
15
14
13
12
Autobias circuit
Pulse generation circuit Clock driver 1 2 Output circuit, S/H circuit Bias circuit (B)
S/H
CCD (905.5bit)
Bias circuit (A)
1
2
3
4
5
6
7
8
9
VSS
VSS
NC
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol IS AB NC IN VDD VSS VGGA OUT VSS VGGB VSS NC VDD NC VSS CLK VDD NC NC SUB I/O O O -- I -- -- O O -- O -- -- -- -- -- I -- -- -- -- GND -2- GND Clock input 5V power supply (For digital system) 4k to 50k 5V power supply (For analog system) Signal input (Negative phase signal) 5V power supply (For clock driver) GND Gate bias (A) DC output Signal output (Positive phase signal) GND Gate bias (B) DC output GND 2k to 10k 2k to 10k 40 to 500 > 100k (at no clamp) Description CCD bias DC output Autobias DC output Impedance [] 600 to 2k 2k to 20k
VGGA
VGGB
NC
AB
VDD
OUT
IS
IN
CXL1504M
Electrical Characteristics (Ta = 25C, VDD = 5V, fCLK = 14.318182MHz, VCLK = 500mVp-p, sine wave) See the Electrical Characteristics Test Circuits. Item Supply current Low frequency gain Frequency response Differential gain Differential phase S/H pulse coupling S/N ratio Symbol IDD Test conditions -- 200kHz, 500mVp-p, sine wave SW conditions 1 a 2 a 3 (Note 1) Bias conditions Min. 4 VBIAS1 [V] -- 20 Typ. Max. 32 42 Unit mA Note 2
a--
GL
a
a
a
b
--
-5.0
-3.0
-1.0
dB
3
fr
200kHz 3.58MHz, b 150mVp-p, c sine wave 5-staircase wave (See Note 5) 5-staircase wave (See Note 5) No signal input 50% white video signal (See Note 7) d d

a
b
b
VIN - 0.2
-2.5
-1.3
0
dB
4
DG DP CP
a a
a a b
c c a
-- -- VIN
0 0 --
3 3 200
7 7
% degree
5 5 6
--b
350 mVp-p
S/N
e
a
a
d
--
54
56
--
dB
7
Notes 1) VIN is defined as follows. VIN is the input signal clamp level, it clamps the video signal sync tip level.
CXL1504 4 Input (IN) Clamp level VIN Negative phase signal input
VIN is the pin voltage for Pin 4 at no-input signal. Testing is executed with a voltmeter under the follwing SW conditions. Item VIN SW conditions 1 -- 2 b 3 a 4 -- V1 Test point
As VIN varies with each IC, they are all subject to testing. 2) IDD is the IC supply current value during clock and signal input. 3) GL is the OUT pin output gain when a 500mVp-p, 200kHz sine wave is input to IN pin. GL = 20 log OUT pin output voltage [mVp-p] 500 [mVp-p] [dB] -3-
CXL1504M
4) Indicates the dissipation at 3.58MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 3.58MHz sine wave is fed to same, calculation is made according to the following formula. The input part bias is tested at VIN - 0.2V. fr = 20 log OUT pin output voltage (3.58MHz) [mVp-p] OUT pin output voltage (200kHz) [mVp-p] [dB]
5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure. below is input are tested at the vector scope.
143mV
357mV 500mV
143mV 1H 63.56s
IN pin input waveform is the inverted waveform in the figure above 6) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input part bias is tested at VINV.
Test value (mVp-p)
7) S/N ratio during 50% white video signal input shown in figure. below is tested at a video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode.
178mV 321mV 143mV 1H 63.56s
IN pin input waveform is the inverted waveform in the figure above
Clock
4fsc (14.318182MHz) sine wave
0.3Vp-p to 1.0Vp-p (0.5Vp-p typ.)
-4-
Electrical Characteristics Test Circuit
CLK 4fsc (14.318182MHz) 0.5Vp-p sine wave
0.1 a 0.01 b 3.3 SW4 16 11 15 14 12 13 9V 20 19 18 17 3.3 0.01
OscilloOscilloscope scope Spectrum analyzer
200kHz 500mVp-p sine wave
a
b
NC
NC
NC
VSS
NC
VDD
VSS
VDD
SW1 c CXL1504M 1.2k
a
-1
SW2
SUB
CLK
200kHz 150mVp-p sine wave
c
Note 1) x 3 LPF
Vector scope d Note 2) x 3 BPF
IN
IS
NC
VSS
VDD
OUT
VSS
AB
VGGA
VGGB
3.58MHz 150mVp-p sine wave 1 2 3 8 3.3 1 0.01 1 4 10 5 7 1 6 9
b
1
Noise meter
5-staircase wave 1
d
-5-
1M ba 5V V1 [dB] 0 -3 -50 0 6M Frequency [Hz]
50% white video signal
e
SW3
51k
Note 1) LPF frequency response [dB] 0 -3
Note 2) BPF frequency response
VBIAS1
-50 14.3M 0 200 6M Frequency [Hz] 14.3M
CXL1504M
Application Circuit
14.318182MHz 0.5Vp-p sine wave
0.1 0.01 3.3 20 11 1.2k 19 18 17 16 15 12 14 13 0.01 3.3 9V
1 CXL1504M
-6-
1 2 3 8 3.3 1 0.01 1M 1 4 5 7 1 6 9 1 5V
Signal input (Negative phase signal)
10
Signal output (Positive phase signal) Transistor used PNP. 2SA1175
CXL1504M
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXL1504M
Example of Representative Characteristics
Low frequency gain vs. Supply voltage
-1
Frequency response vs. Supply voltage
Low frequency gain [dB]
-2
Frequency response [dB]
0
-1
-3
-2
-4
-3 -5 4.75 5.0 Supply voltage [V] 5.25 4.75 5.0 Supply voltage [V] 5.25
Differential gain vs. Supply voltage
10 40
Supply current vs. Supply voltage
8
6
Supply current [mA]
Differential gain [%]
30
4
2
0 4.75
5.0 Supply voltage [V]
5.25
20 4.75
5.0 Supply voltage [V]
5.25
Low frequency gain vs. Ambient temperature
-1
Frequency response vs. Ambient temperature
-2
Frequency response [dB]
0 20 40 60 Ambient temperature [C]
0
Low frequency gain [dB]
-1
-3
-2
-4
-3 -5 0 20 40 60 Ambient temperature [C]
-7-
CXL1504M
Differentical gain vs. Ambient temperature
10
Supply current vs. Ambient temperature
40
8
Differential gain [%]
6
Supply current [mA]
0 20 40 60 Ambient temperature [C]
30
4
3
0
20
0
20 40 60 Ambient temperature [C]
Frequency response
0
-2
Gain [dB]
-4
-6
-8 10k 100k Frequency [Hz] 1M 10M
-8-
CXL1504M
Package Outline
Unit: mm
20PIN SOP (PLASTIC)
+ 0.4 12.45 - 0.1 20 11
+ 0.4 1.85 - 0.15
0.15
+ 0.3 5.3 - 0.1
7.9 0.4
+ 0.2 0.1 - 0.05
1.27
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-20P-L01 SOP020-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.3g
-9-
0.5 0.2
1 0.45 0.1
10
6.9
+ 0.1 0.2 - 0.05

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